/* Copyright Statement:
 *
 * This software/firmware and related documentation ("MediaTek Software") are
 * protected under relevant copyright laws. The information contained herein is
 * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
 * the prior written permission of MediaTek inc. and/or its licensors, any
 * reproduction, modification, use or disclosure of MediaTek Software, and
 * information contained herein, in whole or in part, shall be strictly
 * prohibited.
 *
 * MediaTek Inc. (C) 2019. All rights reserved.
 *
 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
 * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
 * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
 * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
 * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
 * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
 * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
 * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
 * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
 * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
 * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
 * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
 * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
 * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
 * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
 * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
 * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
 *
 * The following software/firmware and/or related documentation ("MediaTek
 * Software") have been modified by MediaTek Inc. All revisions are subject to
 * any receiver's applicable license agreements with MediaTek Inc.
 */
#ifndef __PMIC_WRAP_REGS_H__
#define __PMIC_WRAP_REGS_H__

// APB Module pmif
#define PMIF_SPI_PMIF_INIT_DONE	((u32)(PMIF_SPI_BASE+0x0))
#define PMIF_SPI_PMIF_SWRST	((u32)(PMIF_SPI_BASE+0x4))
#define PMIF_SPI_PMIF_DCM_CTRL	((u32)(PMIF_SPI_BASE+0x8))
#define PMIF_SPI_PMIF_DCM_STA	((u32)(PMIF_SPI_BASE+0xC))
#define PMIF_SPI_PMIF_INF_CK_DCM_EN	((u32)(PMIF_SPI_BASE+0x10))
#define PMIF_SPI_PMIF_OTHER_CK_DCM_EN	((u32)(PMIF_SPI_BASE+0x14))
#define PMIF_SPI_PMIF_INF_BUSY_STA	((u32)(PMIF_SPI_BASE+0x18))
#define PMIF_SPI_PMIF_OTHER_BUSY_STA_0	((u32)(PMIF_SPI_BASE+0x1C))
#define PMIF_SPI_PMIF_OTHER_BUSY_STA_1	((u32)(PMIF_SPI_BASE+0x20))
#define PMIF_SPI_PMIF_INF_EN	((u32)(PMIF_SPI_BASE+0x24))
#define PMIF_SPI_PMIF_OTHER_INF_EN	((u32)(PMIF_SPI_BASE+0x28))
#define PMIF_SPI_PMIF_INF_CMD_PER_0	((u32)(PMIF_SPI_BASE+0x2C))
#define PMIF_SPI_PMIF_INF_CMD_PER_1	((u32)(PMIF_SPI_BASE+0x30))
#define PMIF_SPI_PMIF_INF_CMD_PER_2	((u32)(PMIF_SPI_BASE+0x34))
#define PMIF_SPI_PMIF_INF_CMD_PER_3	((u32)(PMIF_SPI_BASE+0x38))
#define PMIF_SPI_PMIF_INF_MAX_BYTECNT_PER_0	((u32)(PMIF_SPI_BASE+0x3C))
#define PMIF_SPI_PMIF_INF_MAX_BYTECNT_PER_1	((u32)(PMIF_SPI_BASE+0x40))
#define PMIF_SPI_PMIF_INF_MAX_BYTECNT_PER_2	((u32)(PMIF_SPI_BASE+0x44))
#define PMIF_SPI_PMIF_INF_MAX_BYTECNT_PER_3	((u32)(PMIF_SPI_BASE+0x48))
#define PMIF_SPI_PMIF_STAUPD_CTRL	((u32)(PMIF_SPI_BASE+0x4C))
#define PMIF_SPI_PMIF_STAUPD_MAN_TRIG	((u32)(PMIF_SPI_BASE+0x50))
#define PMIF_SPI_PMIF_STAUPD_STA_0	((u32)(PMIF_SPI_BASE+0x54))
#define PMIF_SPI_PMIF_STAUPD_STA_1	((u32)(PMIF_SPI_BASE+0x58))
#define PMIF_SPI_PMIF_DCXO_CMD_ADDR_0	((u32)(PMIF_SPI_BASE+0x5C))
#define PMIF_SPI_PMIF_DCXO_CMD_WDATA_0	((u32)(PMIF_SPI_BASE+0x60))
#define PMIF_SPI_PMIF_DCXO_CMD_ADDR_1	((u32)(PMIF_SPI_BASE+0x64))
#define PMIF_SPI_PMIF_DCXO_CMD_WDATA_1	((u32)(PMIF_SPI_BASE+0x68))
#define PMIF_SPI_PMIF_DCXOINF0_STA	((u32)(PMIF_SPI_BASE+0x6C))
#define PMIF_SPI_PMIF_DCXOINF1_STA	((u32)(PMIF_SPI_BASE+0x70))
#define PMIF_SPI_PMIF_MDADCINF_CTRL	((u32)(PMIF_SPI_BASE+0x74))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_LATEST_ADDR	((u32)(PMIF_SPI_BASE+0x78))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_WP_ADDR	((u32)(PMIF_SPI_BASE+0x7C))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_0_ADDR	((u32)(PMIF_SPI_BASE+0x80))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_1_ADDR	((u32)(PMIF_SPI_BASE+0x84))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_2_ADDR	((u32)(PMIF_SPI_BASE+0x88))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_3_ADDR	((u32)(PMIF_SPI_BASE+0x8C))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_4_ADDR	((u32)(PMIF_SPI_BASE+0x90))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_5_ADDR	((u32)(PMIF_SPI_BASE+0x94))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_6_ADDR	((u32)(PMIF_SPI_BASE+0x98))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_7_ADDR	((u32)(PMIF_SPI_BASE+0x9C))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_8_ADDR	((u32)(PMIF_SPI_BASE+0xA0))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_9_ADDR	((u32)(PMIF_SPI_BASE+0xA4))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_10_ADDR	((u32)(PMIF_SPI_BASE+0xA8))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_11_ADDR	((u32)(PMIF_SPI_BASE+0xAC))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_12_ADDR	((u32)(PMIF_SPI_BASE+0xB0))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_13_ADDR	((u32)(PMIF_SPI_BASE+0xB4))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_14_ADDR	((u32)(PMIF_SPI_BASE+0xB8))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_15_ADDR	((u32)(PMIF_SPI_BASE+0xBC))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_16_ADDR	((u32)(PMIF_SPI_BASE+0xC0))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_17_ADDR	((u32)(PMIF_SPI_BASE+0xC4))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_18_ADDR	((u32)(PMIF_SPI_BASE+0xC8))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_19_ADDR	((u32)(PMIF_SPI_BASE+0xCC))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_20_ADDR	((u32)(PMIF_SPI_BASE+0xD0))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_21_ADDR	((u32)(PMIF_SPI_BASE+0xD4))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_22_ADDR	((u32)(PMIF_SPI_BASE+0xD8))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_23_ADDR	((u32)(PMIF_SPI_BASE+0xDC))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_24_ADDR	((u32)(PMIF_SPI_BASE+0xE0))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_25_ADDR	((u32)(PMIF_SPI_BASE+0xE4))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_26_ADDR	((u32)(PMIF_SPI_BASE+0xE8))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_27_ADDR	((u32)(PMIF_SPI_BASE+0xEC))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_28_ADDR	((u32)(PMIF_SPI_BASE+0xF0))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_29_ADDR	((u32)(PMIF_SPI_BASE+0xF4))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_30_ADDR	((u32)(PMIF_SPI_BASE+0xF8))
#define PMIF_SPI_PMIF_MD_AUXADC_RDATA_31_ADDR	((u32)(PMIF_SPI_BASE+0xFC))
#define PMIF_SPI_PMIF_MDADCINF0_STA_0	((u32)(PMIF_SPI_BASE+0x100))
#define PMIF_SPI_PMIF_MDADCINF0_STA_1	((u32)(PMIF_SPI_BASE+0x104))
#define PMIF_SPI_PMIF_MDADCINF1_STA_0	((u32)(PMIF_SPI_BASE+0x108))
#define PMIF_SPI_PMIF_MDADCINF1_STA_1	((u32)(PMIF_SPI_BASE+0x10C))
#define PMIF_SPI_PMIF_INT_GPS_AUXADC_CMD_ADDR	((u32)(PMIF_SPI_BASE+0x110))
#define PMIF_SPI_PMIF_INT_GPS_AUXADC_CMD	((u32)(PMIF_SPI_BASE+0x114))
#define PMIF_SPI_PMIF_INT_GPS_AUXADC_RDATA_ADDR	((u32)(PMIF_SPI_BASE+0x118))
#define PMIF_SPI_PMIF_INTGPSADCINF0_STA	((u32)(PMIF_SPI_BASE+0x11C))
#define PMIF_SPI_PMIF_INTGPSADCINF1_STA	((u32)(PMIF_SPI_BASE+0x120))
#define PMIF_SPI_PMIF_EXT_GPS_AUXADC_RDATA_ADDR	((u32)(PMIF_SPI_BASE+0x124))
#define PMIF_SPI_PMIF_EXTGPSADCINF_STA	((u32)(PMIF_SPI_BASE+0x128))
#define PMIF_SPI_PMIF_REQCTRL_STA_0	((u32)(PMIF_SPI_BASE+0x12C))
#define PMIF_SPI_PMIF_REQCTRL_STA_1	((u32)(PMIF_SPI_BASE+0x130))
#define PMIF_SPI_PMIF_REQCTRL_STA_2	((u32)(PMIF_SPI_BASE+0x134))
#define PMIF_SPI_PMIF_REQCTRL_STA_3	((u32)(PMIF_SPI_BASE+0x138))
#define PMIF_SPI_PMIF_REQCTRL_STA_4	((u32)(PMIF_SPI_BASE+0x13C))
#define PMIF_SPI_PMIF_REQCTRL_STA_5	((u32)(PMIF_SPI_BASE+0x140))
#define PMIF_SPI_PMIF_REQCTRL_STA_6	((u32)(PMIF_SPI_BASE+0x144))
#define PMIF_SPI_PMIF_REQCTRL_STA_7	((u32)(PMIF_SPI_BASE+0x148))
#define PMIF_SPI_PMIF_REQCTRL_STA_8	((u32)(PMIF_SPI_BASE+0x14C))
#define PMIF_SPI_PMIF_ARB_EN	((u32)(PMIF_SPI_BASE+0x150))
#define PMIF_SPI_PMIF_ARB_MODE	((u32)(PMIF_SPI_BASE+0x154))
#define PMIF_SPI_PMIF_HIGH_PRIO	((u32)(PMIF_SPI_BASE+0x158))
#define PMIF_SPI_PMIF_PRIO_NO_0	((u32)(PMIF_SPI_BASE+0x15C))
#define PMIF_SPI_PMIF_PRIO_NO_1	((u32)(PMIF_SPI_BASE+0x160))
#define PMIF_SPI_PMIF_PRIO_NO_2	((u32)(PMIF_SPI_BASE+0x164))
#define PMIF_SPI_PMIF_PRIO_NO_3	((u32)(PMIF_SPI_BASE+0x168))
#define PMIF_SPI_PMIF_PRIO_NO_4	((u32)(PMIF_SPI_BASE+0x16C))
#define PMIF_SPI_PMIF_PRIO_NO_5	((u32)(PMIF_SPI_BASE+0x170))
#define PMIF_SPI_PMIF_PRIO_NO_6	((u32)(PMIF_SPI_BASE+0x174))
#define PMIF_SPI_PMIF_PRIO_NO_7	((u32)(PMIF_SPI_BASE+0x178))
#define PMIF_SPI_PMIF_PRIO_NO_8	((u32)(PMIF_SPI_BASE+0x17C))
#define PMIF_SPI_PMIF_PRIO_NO_9	((u32)(PMIF_SPI_BASE+0x180))
#define PMIF_SPI_PMIF_PRIO_NO_10	((u32)(PMIF_SPI_BASE+0x184))
#define PMIF_SPI_PMIF_PRIO_NO_11	((u32)(PMIF_SPI_BASE+0x188))
#define PMIF_SPI_PMIF_PRIO_NO_12	((u32)(PMIF_SPI_BASE+0x18C))
#define PMIF_SPI_PMIF_PRIO_NO_13	((u32)(PMIF_SPI_BASE+0x190))
#define PMIF_SPI_PMIF_PRIO_NO_14	((u32)(PMIF_SPI_BASE+0x194))
#define PMIF_SPI_PMIF_PRIO_NO_15	((u32)(PMIF_SPI_BASE+0x198))
#define PMIF_SPI_PMIF_PRIO_NO_16	((u32)(PMIF_SPI_BASE+0x19C))
#define PMIF_SPI_PMIF_PRIO_NO_17	((u32)(PMIF_SPI_BASE+0x1A0))
#define PMIF_SPI_PMIF_PRIO_NO_18	((u32)(PMIF_SPI_BASE+0x1A4))
#define PMIF_SPI_PMIF_PRIO_NO_19	((u32)(PMIF_SPI_BASE+0x1A8))
#define PMIF_SPI_PMIF_PRIO_NO_20	((u32)(PMIF_SPI_BASE+0x1AC))
#define PMIF_SPI_PMIF_PRIO_NO_21	((u32)(PMIF_SPI_BASE+0x1B0))
#define PMIF_SPI_PMIF_PRIO_NO_22	((u32)(PMIF_SPI_BASE+0x1B4))
#define PMIF_SPI_PMIF_PRIO_NO_23	((u32)(PMIF_SPI_BASE+0x1B8))
#define PMIF_SPI_PMIF_PRIO_NO_24	((u32)(PMIF_SPI_BASE+0x1BC))
#define PMIF_SPI_PMIF_PRIO_NO_25	((u32)(PMIF_SPI_BASE+0x1C0))
#define PMIF_SPI_PMIF_PRIO_NO_26	((u32)(PMIF_SPI_BASE+0x1C4))
#define PMIF_SPI_PMIF_PRIO_NO_27	((u32)(PMIF_SPI_BASE+0x1C8))
#define PMIF_SPI_PMIF_PRIO_NO_28	((u32)(PMIF_SPI_BASE+0x1CC))
#define PMIF_SPI_PMIF_PRIO_NO_29	((u32)(PMIF_SPI_BASE+0x1D0))
#define PMIF_SPI_PMIF_PRIO_NO_30	((u32)(PMIF_SPI_BASE+0x1D4))
#define PMIF_SPI_PMIF_PRIO_NO_31	((u32)(PMIF_SPI_BASE+0x1D8))
#define PMIF_SPI_PMIF_LAT_CNTER_CTRL	((u32)(PMIF_SPI_BASE+0x1DC))
#define PMIF_SPI_PMIF_LAT_CNTER_EN	((u32)(PMIF_SPI_BASE+0x1E0))
#define PMIF_SPI_PMIF_LAT_LIMIT_LOADING	((u32)(PMIF_SPI_BASE+0x1E4))
#define PMIF_SPI_PMIF_LAT_LIMIT_0	((u32)(PMIF_SPI_BASE+0x1E8))
#define PMIF_SPI_PMIF_LAT_LIMIT_1	((u32)(PMIF_SPI_BASE+0x1EC))
#define PMIF_SPI_PMIF_LAT_LIMIT_2	((u32)(PMIF_SPI_BASE+0x1F0))
#define PMIF_SPI_PMIF_LAT_LIMIT_3	((u32)(PMIF_SPI_BASE+0x1F4))
#define PMIF_SPI_PMIF_LAT_LIMIT_4	((u32)(PMIF_SPI_BASE+0x1F8))
#define PMIF_SPI_PMIF_LAT_LIMIT_5	((u32)(PMIF_SPI_BASE+0x1FC))
#define PMIF_SPI_PMIF_LAT_LIMIT_6	((u32)(PMIF_SPI_BASE+0x200))
#define PMIF_SPI_PMIF_LAT_LIMIT_7	((u32)(PMIF_SPI_BASE+0x204))
#define PMIF_SPI_PMIF_LAT_LIMIT_8	((u32)(PMIF_SPI_BASE+0x208))
#define PMIF_SPI_PMIF_LAT_LIMIT_9	((u32)(PMIF_SPI_BASE+0x20C))
#define PMIF_SPI_PMIF_LAT_LIMIT_10	((u32)(PMIF_SPI_BASE+0x210))
#define PMIF_SPI_PMIF_LAT_LIMIT_11	((u32)(PMIF_SPI_BASE+0x214))
#define PMIF_SPI_PMIF_LAT_LIMIT_12	((u32)(PMIF_SPI_BASE+0x218))
#define PMIF_SPI_PMIF_LAT_LIMIT_13	((u32)(PMIF_SPI_BASE+0x21C))
#define PMIF_SPI_PMIF_LAT_LIMIT_14	((u32)(PMIF_SPI_BASE+0x220))
#define PMIF_SPI_PMIF_LAT_LIMIT_15	((u32)(PMIF_SPI_BASE+0x224))
#define PMIF_SPI_PMIF_LAT_LIMIT_16	((u32)(PMIF_SPI_BASE+0x228))
#define PMIF_SPI_PMIF_LAT_LIMIT_17	((u32)(PMIF_SPI_BASE+0x22C))
#define PMIF_SPI_PMIF_LAT_LIMIT_18	((u32)(PMIF_SPI_BASE+0x230))
#define PMIF_SPI_PMIF_LAT_LIMIT_19	((u32)(PMIF_SPI_BASE+0x234))
#define PMIF_SPI_PMIF_LAT_LIMIT_20	((u32)(PMIF_SPI_BASE+0x238))
#define PMIF_SPI_PMIF_LAT_LIMIT_21	((u32)(PMIF_SPI_BASE+0x23C))
#define PMIF_SPI_PMIF_LAT_LIMIT_22	((u32)(PMIF_SPI_BASE+0x240))
#define PMIF_SPI_PMIF_LAT_LIMIT_23	((u32)(PMIF_SPI_BASE+0x244))
#define PMIF_SPI_PMIF_LAT_LIMIT_24	((u32)(PMIF_SPI_BASE+0x248))
#define PMIF_SPI_PMIF_LAT_LIMIT_25	((u32)(PMIF_SPI_BASE+0x24C))
#define PMIF_SPI_PMIF_LAT_LIMIT_26	((u32)(PMIF_SPI_BASE+0x250))
#define PMIF_SPI_PMIF_LAT_LIMIT_27	((u32)(PMIF_SPI_BASE+0x254))
#define PMIF_SPI_PMIF_LAT_LIMIT_28	((u32)(PMIF_SPI_BASE+0x258))
#define PMIF_SPI_PMIF_LAT_LIMIT_29	((u32)(PMIF_SPI_BASE+0x25C))
#define PMIF_SPI_PMIF_LAT_LIMIT_30	((u32)(PMIF_SPI_BASE+0x260))
#define PMIF_SPI_PMIF_LAT_LIMIT_31	((u32)(PMIF_SPI_BASE+0x264))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_0	((u32)(PMIF_SPI_BASE+0x268))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_1	((u32)(PMIF_SPI_BASE+0x26C))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_2	((u32)(PMIF_SPI_BASE+0x270))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_3	((u32)(PMIF_SPI_BASE+0x274))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_4	((u32)(PMIF_SPI_BASE+0x278))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_5	((u32)(PMIF_SPI_BASE+0x27C))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_6	((u32)(PMIF_SPI_BASE+0x280))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_7	((u32)(PMIF_SPI_BASE+0x284))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_8	((u32)(PMIF_SPI_BASE+0x288))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_9	((u32)(PMIF_SPI_BASE+0x28C))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_10	((u32)(PMIF_SPI_BASE+0x290))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_11	((u32)(PMIF_SPI_BASE+0x294))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_12	((u32)(PMIF_SPI_BASE+0x298))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_13	((u32)(PMIF_SPI_BASE+0x29C))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_14	((u32)(PMIF_SPI_BASE+0x2A0))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_15	((u32)(PMIF_SPI_BASE+0x2A4))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_16	((u32)(PMIF_SPI_BASE+0x2A8))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_17	((u32)(PMIF_SPI_BASE+0x2AC))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_18	((u32)(PMIF_SPI_BASE+0x2B0))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_19	((u32)(PMIF_SPI_BASE+0x2B4))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_20	((u32)(PMIF_SPI_BASE+0x2B8))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_21	((u32)(PMIF_SPI_BASE+0x2BC))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_22	((u32)(PMIF_SPI_BASE+0x2C0))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_23	((u32)(PMIF_SPI_BASE+0x2C4))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_24	((u32)(PMIF_SPI_BASE+0x2C8))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_25	((u32)(PMIF_SPI_BASE+0x2CC))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_26	((u32)(PMIF_SPI_BASE+0x2D0))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_27	((u32)(PMIF_SPI_BASE+0x2D4))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_28	((u32)(PMIF_SPI_BASE+0x2D8))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_29	((u32)(PMIF_SPI_BASE+0x2DC))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_30	((u32)(PMIF_SPI_BASE+0x2E0))
#define PMIF_SPI_PMIF_LAT_CNTER_STA_31	((u32)(PMIF_SPI_BASE+0x2E4))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORDING_CTRL	((u32)(PMIF_SPI_BASE+0x2E8))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_CLR	((u32)(PMIF_SPI_BASE+0x2EC))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_0	((u32)(PMIF_SPI_BASE+0x2F0))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_1	((u32)(PMIF_SPI_BASE+0x2F4))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_2	((u32)(PMIF_SPI_BASE+0x2F8))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_3	((u32)(PMIF_SPI_BASE+0x2FC))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_4	((u32)(PMIF_SPI_BASE+0x300))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_5	((u32)(PMIF_SPI_BASE+0x304))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_6	((u32)(PMIF_SPI_BASE+0x308))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_7	((u32)(PMIF_SPI_BASE+0x30C))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_8	((u32)(PMIF_SPI_BASE+0x310))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_9	((u32)(PMIF_SPI_BASE+0x314))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_10	((u32)(PMIF_SPI_BASE+0x318))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_11	((u32)(PMIF_SPI_BASE+0x31C))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_12	((u32)(PMIF_SPI_BASE+0x320))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_13	((u32)(PMIF_SPI_BASE+0x324))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_14	((u32)(PMIF_SPI_BASE+0x328))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_15	((u32)(PMIF_SPI_BASE+0x32C))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_16	((u32)(PMIF_SPI_BASE+0x330))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_17	((u32)(PMIF_SPI_BASE+0x334))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_18	((u32)(PMIF_SPI_BASE+0x338))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_19	((u32)(PMIF_SPI_BASE+0x33C))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_20	((u32)(PMIF_SPI_BASE+0x340))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_21	((u32)(PMIF_SPI_BASE+0x344))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_22	((u32)(PMIF_SPI_BASE+0x348))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_23	((u32)(PMIF_SPI_BASE+0x34C))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_24	((u32)(PMIF_SPI_BASE+0x350))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_25	((u32)(PMIF_SPI_BASE+0x354))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_26	((u32)(PMIF_SPI_BASE+0x358))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_27	((u32)(PMIF_SPI_BASE+0x35C))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_28	((u32)(PMIF_SPI_BASE+0x360))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_29	((u32)(PMIF_SPI_BASE+0x364))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_30	((u32)(PMIF_SPI_BASE+0x368))
#define PMIF_SPI_PMIF_LAT_CNTER_RECORD_31	((u32)(PMIF_SPI_BASE+0x36C))
#define PMIF_SPI_PMIF_LAT_LIMIT_REACHED_INT_EN	((u32)(PMIF_SPI_BASE+0x370))
#define PMIF_SPI_PMIF_ARBITER_STA_0	((u32)(PMIF_SPI_BASE+0x374))
#define PMIF_SPI_PMIF_ARBITER_STA_1	((u32)(PMIF_SPI_BASE+0x378))
#define PMIF_SPI_PMIF_ARBITER_STA_2	((u32)(PMIF_SPI_BASE+0x37C))
#define PMIF_SPI_PMIF_ARBITER_STA_3	((u32)(PMIF_SPI_BASE+0x380))
#define PMIF_SPI_PMIF_ARBITER_STA_4	((u32)(PMIF_SPI_BASE+0x384))
#define PMIF_SPI_PMIF_ARBITER_STA_5	((u32)(PMIF_SPI_BASE+0x388))
#define PMIF_SPI_PMIF_ARBITER_STA_6	((u32)(PMIF_SPI_BASE+0x38C))
#define PMIF_SPI_PMIF_ARBITER_STA_7	((u32)(PMIF_SPI_BASE+0x390))
#define PMIF_SPI_PMIF_ARBITER_STA_8	((u32)(PMIF_SPI_BASE+0x394))
#define PMIF_SPI_PMIF_ARBITER_STA_9	((u32)(PMIF_SPI_BASE+0x398))
#define PMIF_SPI_PMIF_CRC_CTRL	((u32)(PMIF_SPI_BASE+0x39C))
#define PMIF_SPI_PMIF_CRC_STA	((u32)(PMIF_SPI_BASE+0x3A0))
#define PMIF_SPI_PMIF_SIG_MODE	((u32)(PMIF_SPI_BASE+0x3A4))
#define PMIF_SPI_PMIF_PMIC_SIG_ADDR	((u32)(PMIF_SPI_BASE+0x3A8))
#define PMIF_SPI_PMIF_PMIC_SIG_VAL	((u32)(PMIF_SPI_BASE+0x3AC))
#define PMIF_SPI_PMIF_PMIC_SIG_ERR_VAL	((u32)(PMIF_SPI_BASE+0x3B0))
#define PMIF_SPI_PMIF_SIG_ERR_VAL	((u32)(PMIF_SPI_BASE+0x3B4))
#define PMIF_SPI_PMIF_CMDISSUE_EN	((u32)(PMIF_SPI_BASE+0x3B8))
#define PMIF_SPI_PMIF_CMDISSUE_STA_0	((u32)(PMIF_SPI_BASE+0x3BC))
#define PMIF_SPI_PMIF_CMDISSUE_STA_1	((u32)(PMIF_SPI_BASE+0x3C0))
#define PMIF_SPI_PMIF_CMDISSUE_STA_2	((u32)(PMIF_SPI_BASE+0x3C4))
#define PMIF_SPI_PMIF_CMDISSUE_STA_3	((u32)(PMIF_SPI_BASE+0x3C8))
#define PMIF_SPI_PMIF_CMDISSUE_STA_4	((u32)(PMIF_SPI_BASE+0x3CC))
#define PMIF_SPI_PMIF_CMDISSUE_STA_5	((u32)(PMIF_SPI_BASE+0x3D0))
#define PMIF_SPI_PMIF_CMDISSUE_STA_6	((u32)(PMIF_SPI_BASE+0x3D4))
#define PMIF_SPI_PMIF_CMDISSUE_STA_7	((u32)(PMIF_SPI_BASE+0x3D8))
#define PMIF_SPI_PMIF_CMDISSUE_STA_8	((u32)(PMIF_SPI_BASE+0x3DC))
#define PMIF_SPI_PMIF_CMDISSUE_STA_9	((u32)(PMIF_SPI_BASE+0x3E0))
#define PMIF_SPI_PMIF_TIMER_CTRL	((u32)(PMIF_SPI_BASE+0x3E4))
#define PMIF_SPI_PMIF_TIMER_STA_0	((u32)(PMIF_SPI_BASE+0x3E8))
#define PMIF_SPI_PMIF_TIMER_STA_1	((u32)(PMIF_SPI_BASE+0x3EC))
#define PMIF_SPI_PMIF_SLEEP_PROTECTION_CTRL	((u32)(PMIF_SPI_BASE+0x3F0))
#define PMIF_SPI_PMIF_SPM_SLEEP_GATING_EN	((u32)(PMIF_SPI_BASE+0x3F4))
#define PMIF_SPI_PMIF_SCP_SLEEP_GATING_EN	((u32)(PMIF_SPI_BASE+0x3F8))
#define PMIF_SPI_PMIF_SPM_SLEEPINF_STA	((u32)(PMIF_SPI_BASE+0x3FC))
#define PMIF_SPI_PMIF_SCP_SLEEPINF_STA	((u32)(PMIF_SPI_BASE+0x400))
#define PMIF_SPI_PMIF_PMICEINTREQINF_STA	((u32)(PMIF_SPI_BASE+0x404))
#define PMIF_SPI_PMIF_SPI_MODE_CTRL	((u32)(PMIF_SPI_BASE+0x408))
#define PMIF_SPI_PMIF_SPIMODE_STA	((u32)(PMIF_SPI_BASE+0x40C))
#define PMIF_SPI_PMIF_PMIC_EINT_CTRL	((u32)(PMIF_SPI_BASE+0x410))
#define PMIF_SPI_PMIF_PMIC_EINT_STA_ADDR	((u32)(PMIF_SPI_BASE+0x414))
#define PMIF_SPI_PMIF_PMIC_EINT_STA	((u32)(PMIF_SPI_BASE+0x418))
#define PMIF_SPI_PMIF_PMIC_EINT_CLR	((u32)(PMIF_SPI_BASE+0x41C))
#define PMIF_SPI_PMIF_IRQ_EVENT_EN_0	((u32)(PMIF_SPI_BASE+0x420))
#define PMIF_SPI_PMIF_IRQ_FLAG_RAW_0	((u32)(PMIF_SPI_BASE+0x424))
#define PMIF_SPI_PMIF_IRQ_FLAG_0	((u32)(PMIF_SPI_BASE+0x428))
#define PMIF_SPI_PMIF_IRQ_CLR_0	((u32)(PMIF_SPI_BASE+0x42C))
#define PMIF_SPI_PMIF_IRQ_EVENT_EN_1	((u32)(PMIF_SPI_BASE+0x430))
#define PMIF_SPI_PMIF_IRQ_FLAG_RAW_1	((u32)(PMIF_SPI_BASE+0x434))
#define PMIF_SPI_PMIF_IRQ_FLAG_1	((u32)(PMIF_SPI_BASE+0x438))
#define PMIF_SPI_PMIF_IRQ_CLR_1	((u32)(PMIF_SPI_BASE+0x43C))
#define PMIF_SPI_PMIF_IRQ_EVENT_EN_2	((u32)(PMIF_SPI_BASE+0x440))
#define PMIF_SPI_PMIF_IRQ_FLAG_RAW_2	((u32)(PMIF_SPI_BASE+0x444))
#define PMIF_SPI_PMIF_IRQ_FLAG_2	((u32)(PMIF_SPI_BASE+0x448))
#define PMIF_SPI_PMIF_IRQ_CLR_2	((u32)(PMIF_SPI_BASE+0x44C))
#define PMIF_SPI_PMIF_IRQ_EVENT_EN_3	((u32)(PMIF_SPI_BASE+0x450))
#define PMIF_SPI_PMIF_IRQ_FLAG_RAW_3	((u32)(PMIF_SPI_BASE+0x454))
#define PMIF_SPI_PMIF_IRQ_FLAG_3	((u32)(PMIF_SPI_BASE+0x458))
#define PMIF_SPI_PMIF_IRQ_CLR_3	((u32)(PMIF_SPI_BASE+0x45C))
#define PMIF_SPI_PMIF_IRQ_EVENT_EN_4	((u32)(PMIF_SPI_BASE+0x460))
#define PMIF_SPI_PMIF_IRQ_FLAG_RAW_4	((u32)(PMIF_SPI_BASE+0x464))
#define PMIF_SPI_PMIF_IRQ_FLAG_4	((u32)(PMIF_SPI_BASE+0x468))
#define PMIF_SPI_PMIF_IRQ_CLR_4	((u32)(PMIF_SPI_BASE+0x46C))
#define PMIF_SPI_PMIF_WDT_CTRL	((u32)(PMIF_SPI_BASE+0x470))
#define PMIF_SPI_PMIF_WDT_EVENT_EN_0	((u32)(PMIF_SPI_BASE+0x474))
#define PMIF_SPI_PMIF_WDT_FLAG_0	((u32)(PMIF_SPI_BASE+0x478))
#define PMIF_SPI_PMIF_WDT_EVENT_EN_1	((u32)(PMIF_SPI_BASE+0x47C))
#define PMIF_SPI_PMIF_WDT_FLAG_1	((u32)(PMIF_SPI_BASE+0x480))
#define PMIF_SPI_PMIF_MONITOR_CTRL	((u32)(PMIF_SPI_BASE+0x484))
#define PMIF_SPI_PMIF_MONITOR_TARGET_CHAN_0	((u32)(PMIF_SPI_BASE+0x488))
#define PMIF_SPI_PMIF_MONITOR_TARGET_CHAN_1	((u32)(PMIF_SPI_BASE+0x48C))
#define PMIF_SPI_PMIF_MONITOR_TARGET_CHAN_2	((u32)(PMIF_SPI_BASE+0x490))
#define PMIF_SPI_PMIF_MONITOR_TARGET_CHAN_3	((u32)(PMIF_SPI_BASE+0x494))
#define PMIF_SPI_PMIF_MONITOR_TARGET_CHAN_4	((u32)(PMIF_SPI_BASE+0x498))
#define PMIF_SPI_PMIF_MONITOR_TARGET_CHAN_5	((u32)(PMIF_SPI_BASE+0x49C))
#define PMIF_SPI_PMIF_MONITOR_TARGET_CHAN_6	((u32)(PMIF_SPI_BASE+0x4A0))
#define PMIF_SPI_PMIF_MONITOR_TARGET_CHAN_7	((u32)(PMIF_SPI_BASE+0x4A4))
#define PMIF_SPI_PMIF_MONITOR_TARGET_WRITE	((u32)(PMIF_SPI_BASE+0x4A8))
#define PMIF_SPI_PMIF_MONITOR_TARGET_SLVID_0	((u32)(PMIF_SPI_BASE+0x4AC))
#define PMIF_SPI_PMIF_MONITOR_TARGET_SLVID_1	((u32)(PMIF_SPI_BASE+0x4B0))
#define PMIF_SPI_PMIF_MONITOR_TARGET_ADDR_0	((u32)(PMIF_SPI_BASE+0x4B4))
#define PMIF_SPI_PMIF_MONITOR_TARGET_ADDR_1	((u32)(PMIF_SPI_BASE+0x4B8))
#define PMIF_SPI_PMIF_MONITOR_TARGET_ADDR_2	((u32)(PMIF_SPI_BASE+0x4BC))
#define PMIF_SPI_PMIF_MONITOR_TARGET_ADDR_3	((u32)(PMIF_SPI_BASE+0x4C0))
#define PMIF_SPI_PMIF_MONITOR_TARGET_ADDR_4	((u32)(PMIF_SPI_BASE+0x4C4))
#define PMIF_SPI_PMIF_MONITOR_TARGET_ADDR_5	((u32)(PMIF_SPI_BASE+0x4C8))
#define PMIF_SPI_PMIF_MONITOR_TARGET_ADDR_6	((u32)(PMIF_SPI_BASE+0x4CC))
#define PMIF_SPI_PMIF_MONITOR_TARGET_ADDR_7	((u32)(PMIF_SPI_BASE+0x4D0))
#define PMIF_SPI_PMIF_MONITOR_TARGET_WDATA_0	((u32)(PMIF_SPI_BASE+0x4D4))
#define PMIF_SPI_PMIF_MONITOR_TARGET_WDATA_1	((u32)(PMIF_SPI_BASE+0x4D8))
#define PMIF_SPI_PMIF_MONITOR_TARGET_WDATA_2	((u32)(PMIF_SPI_BASE+0x4DC))
#define PMIF_SPI_PMIF_MONITOR_TARGET_WDATA_3	((u32)(PMIF_SPI_BASE+0x4E0))
#define PMIF_SPI_PMIF_MONITOR_TARGET_WDATA_4	((u32)(PMIF_SPI_BASE+0x4E4))
#define PMIF_SPI_PMIF_MONITOR_TARGET_WDATA_5	((u32)(PMIF_SPI_BASE+0x4E8))
#define PMIF_SPI_PMIF_MONITOR_TARGET_WDATA_6	((u32)(PMIF_SPI_BASE+0x4EC))
#define PMIF_SPI_PMIF_MONITOR_TARGET_WDATA_7	((u32)(PMIF_SPI_BASE+0x4F0))
#define PMIF_SPI_PMIF_MONITOR_STA	((u32)(PMIF_SPI_BASE+0x4F4))
#define PMIF_SPI_PMIF_MONITOR_RECORD_0_0	((u32)(PMIF_SPI_BASE+0x4F8))
#define PMIF_SPI_PMIF_MONITOR_RECORD_0_1	((u32)(PMIF_SPI_BASE+0x4FC))
#define PMIF_SPI_PMIF_MONITOR_RECORD_0_2	((u32)(PMIF_SPI_BASE+0x500))
#define PMIF_SPI_PMIF_MONITOR_RECORD_0_3	((u32)(PMIF_SPI_BASE+0x504))
#define PMIF_SPI_PMIF_MONITOR_RECORD_0_4	((u32)(PMIF_SPI_BASE+0x508))
#define PMIF_SPI_PMIF_MONITOR_RECORD_1_0	((u32)(PMIF_SPI_BASE+0x50C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_1_1	((u32)(PMIF_SPI_BASE+0x510))
#define PMIF_SPI_PMIF_MONITOR_RECORD_1_2	((u32)(PMIF_SPI_BASE+0x514))
#define PMIF_SPI_PMIF_MONITOR_RECORD_1_3	((u32)(PMIF_SPI_BASE+0x518))
#define PMIF_SPI_PMIF_MONITOR_RECORD_1_4	((u32)(PMIF_SPI_BASE+0x51C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_2_0	((u32)(PMIF_SPI_BASE+0x520))
#define PMIF_SPI_PMIF_MONITOR_RECORD_2_1	((u32)(PMIF_SPI_BASE+0x524))
#define PMIF_SPI_PMIF_MONITOR_RECORD_2_2	((u32)(PMIF_SPI_BASE+0x528))
#define PMIF_SPI_PMIF_MONITOR_RECORD_2_3	((u32)(PMIF_SPI_BASE+0x52C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_2_4	((u32)(PMIF_SPI_BASE+0x530))
#define PMIF_SPI_PMIF_MONITOR_RECORD_3_0	((u32)(PMIF_SPI_BASE+0x534))
#define PMIF_SPI_PMIF_MONITOR_RECORD_3_1	((u32)(PMIF_SPI_BASE+0x538))
#define PMIF_SPI_PMIF_MONITOR_RECORD_3_2	((u32)(PMIF_SPI_BASE+0x53C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_3_3	((u32)(PMIF_SPI_BASE+0x540))
#define PMIF_SPI_PMIF_MONITOR_RECORD_3_4	((u32)(PMIF_SPI_BASE+0x544))
#define PMIF_SPI_PMIF_MONITOR_RECORD_4_0	((u32)(PMIF_SPI_BASE+0x548))
#define PMIF_SPI_PMIF_MONITOR_RECORD_4_1	((u32)(PMIF_SPI_BASE+0x54C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_4_2	((u32)(PMIF_SPI_BASE+0x550))
#define PMIF_SPI_PMIF_MONITOR_RECORD_4_3	((u32)(PMIF_SPI_BASE+0x554))
#define PMIF_SPI_PMIF_MONITOR_RECORD_4_4	((u32)(PMIF_SPI_BASE+0x558))
#define PMIF_SPI_PMIF_MONITOR_RECORD_5_0	((u32)(PMIF_SPI_BASE+0x55C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_5_1	((u32)(PMIF_SPI_BASE+0x560))
#define PMIF_SPI_PMIF_MONITOR_RECORD_5_2	((u32)(PMIF_SPI_BASE+0x564))
#define PMIF_SPI_PMIF_MONITOR_RECORD_5_3	((u32)(PMIF_SPI_BASE+0x568))
#define PMIF_SPI_PMIF_MONITOR_RECORD_5_4	((u32)(PMIF_SPI_BASE+0x56C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_6_0	((u32)(PMIF_SPI_BASE+0x570))
#define PMIF_SPI_PMIF_MONITOR_RECORD_6_1	((u32)(PMIF_SPI_BASE+0x574))
#define PMIF_SPI_PMIF_MONITOR_RECORD_6_2	((u32)(PMIF_SPI_BASE+0x578))
#define PMIF_SPI_PMIF_MONITOR_RECORD_6_3	((u32)(PMIF_SPI_BASE+0x57C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_6_4	((u32)(PMIF_SPI_BASE+0x580))
#define PMIF_SPI_PMIF_MONITOR_RECORD_7_0	((u32)(PMIF_SPI_BASE+0x584))
#define PMIF_SPI_PMIF_MONITOR_RECORD_7_1	((u32)(PMIF_SPI_BASE+0x588))
#define PMIF_SPI_PMIF_MONITOR_RECORD_7_2	((u32)(PMIF_SPI_BASE+0x58C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_7_3	((u32)(PMIF_SPI_BASE+0x590))
#define PMIF_SPI_PMIF_MONITOR_RECORD_7_4	((u32)(PMIF_SPI_BASE+0x594))
#define PMIF_SPI_PMIF_MONITOR_RECORD_8_0	((u32)(PMIF_SPI_BASE+0x598))
#define PMIF_SPI_PMIF_MONITOR_RECORD_8_1	((u32)(PMIF_SPI_BASE+0x59C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_8_2	((u32)(PMIF_SPI_BASE+0x5A0))
#define PMIF_SPI_PMIF_MONITOR_RECORD_8_3	((u32)(PMIF_SPI_BASE+0x5A4))
#define PMIF_SPI_PMIF_MONITOR_RECORD_8_4	((u32)(PMIF_SPI_BASE+0x5A8))
#define PMIF_SPI_PMIF_MONITOR_RECORD_9_0	((u32)(PMIF_SPI_BASE+0x5AC))
#define PMIF_SPI_PMIF_MONITOR_RECORD_9_1	((u32)(PMIF_SPI_BASE+0x5B0))
#define PMIF_SPI_PMIF_MONITOR_RECORD_9_2	((u32)(PMIF_SPI_BASE+0x5B4))
#define PMIF_SPI_PMIF_MONITOR_RECORD_9_3	((u32)(PMIF_SPI_BASE+0x5B8))
#define PMIF_SPI_PMIF_MONITOR_RECORD_9_4	((u32)(PMIF_SPI_BASE+0x5BC))
#define PMIF_SPI_PMIF_MONITOR_RECORD_10_0	((u32)(PMIF_SPI_BASE+0x5C0))
#define PMIF_SPI_PMIF_MONITOR_RECORD_10_1	((u32)(PMIF_SPI_BASE+0x5C4))
#define PMIF_SPI_PMIF_MONITOR_RECORD_10_2	((u32)(PMIF_SPI_BASE+0x5C8))
#define PMIF_SPI_PMIF_MONITOR_RECORD_10_3	((u32)(PMIF_SPI_BASE+0x5CC))
#define PMIF_SPI_PMIF_MONITOR_RECORD_10_4	((u32)(PMIF_SPI_BASE+0x5D0))
#define PMIF_SPI_PMIF_MONITOR_RECORD_11_0	((u32)(PMIF_SPI_BASE+0x5D4))
#define PMIF_SPI_PMIF_MONITOR_RECORD_11_1	((u32)(PMIF_SPI_BASE+0x5D8))
#define PMIF_SPI_PMIF_MONITOR_RECORD_11_2	((u32)(PMIF_SPI_BASE+0x5DC))
#define PMIF_SPI_PMIF_MONITOR_RECORD_11_3	((u32)(PMIF_SPI_BASE+0x5E0))
#define PMIF_SPI_PMIF_MONITOR_RECORD_11_4	((u32)(PMIF_SPI_BASE+0x5E4))
#define PMIF_SPI_PMIF_MONITOR_RECORD_12_0	((u32)(PMIF_SPI_BASE+0x5E8))
#define PMIF_SPI_PMIF_MONITOR_RECORD_12_1	((u32)(PMIF_SPI_BASE+0x5EC))
#define PMIF_SPI_PMIF_MONITOR_RECORD_12_2	((u32)(PMIF_SPI_BASE+0x5F0))
#define PMIF_SPI_PMIF_MONITOR_RECORD_12_3	((u32)(PMIF_SPI_BASE+0x5F4))
#define PMIF_SPI_PMIF_MONITOR_RECORD_12_4	((u32)(PMIF_SPI_BASE+0x5F8))
#define PMIF_SPI_PMIF_MONITOR_RECORD_13_0	((u32)(PMIF_SPI_BASE+0x5FC))
#define PMIF_SPI_PMIF_MONITOR_RECORD_13_1	((u32)(PMIF_SPI_BASE+0x600))
#define PMIF_SPI_PMIF_MONITOR_RECORD_13_2	((u32)(PMIF_SPI_BASE+0x604))
#define PMIF_SPI_PMIF_MONITOR_RECORD_13_3	((u32)(PMIF_SPI_BASE+0x608))
#define PMIF_SPI_PMIF_MONITOR_RECORD_13_4	((u32)(PMIF_SPI_BASE+0x60C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_14_0	((u32)(PMIF_SPI_BASE+0x610))
#define PMIF_SPI_PMIF_MONITOR_RECORD_14_1	((u32)(PMIF_SPI_BASE+0x614))
#define PMIF_SPI_PMIF_MONITOR_RECORD_14_2	((u32)(PMIF_SPI_BASE+0x618))
#define PMIF_SPI_PMIF_MONITOR_RECORD_14_3	((u32)(PMIF_SPI_BASE+0x61C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_14_4	((u32)(PMIF_SPI_BASE+0x620))
#define PMIF_SPI_PMIF_MONITOR_RECORD_15_0	((u32)(PMIF_SPI_BASE+0x624))
#define PMIF_SPI_PMIF_MONITOR_RECORD_15_1	((u32)(PMIF_SPI_BASE+0x628))
#define PMIF_SPI_PMIF_MONITOR_RECORD_15_2	((u32)(PMIF_SPI_BASE+0x62C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_15_3	((u32)(PMIF_SPI_BASE+0x630))
#define PMIF_SPI_PMIF_MONITOR_RECORD_15_4	((u32)(PMIF_SPI_BASE+0x634))
#define PMIF_SPI_PMIF_MONITOR_RECORD_16_0	((u32)(PMIF_SPI_BASE+0x638))
#define PMIF_SPI_PMIF_MONITOR_RECORD_16_1	((u32)(PMIF_SPI_BASE+0x63C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_16_2	((u32)(PMIF_SPI_BASE+0x640))
#define PMIF_SPI_PMIF_MONITOR_RECORD_16_3	((u32)(PMIF_SPI_BASE+0x644))
#define PMIF_SPI_PMIF_MONITOR_RECORD_16_4	((u32)(PMIF_SPI_BASE+0x648))
#define PMIF_SPI_PMIF_MONITOR_RECORD_17_0	((u32)(PMIF_SPI_BASE+0x64C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_17_1	((u32)(PMIF_SPI_BASE+0x650))
#define PMIF_SPI_PMIF_MONITOR_RECORD_17_2	((u32)(PMIF_SPI_BASE+0x654))
#define PMIF_SPI_PMIF_MONITOR_RECORD_17_3	((u32)(PMIF_SPI_BASE+0x658))
#define PMIF_SPI_PMIF_MONITOR_RECORD_17_4	((u32)(PMIF_SPI_BASE+0x65C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_18_0	((u32)(PMIF_SPI_BASE+0x660))
#define PMIF_SPI_PMIF_MONITOR_RECORD_18_1	((u32)(PMIF_SPI_BASE+0x664))
#define PMIF_SPI_PMIF_MONITOR_RECORD_18_2	((u32)(PMIF_SPI_BASE+0x668))
#define PMIF_SPI_PMIF_MONITOR_RECORD_18_3	((u32)(PMIF_SPI_BASE+0x66C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_18_4	((u32)(PMIF_SPI_BASE+0x670))
#define PMIF_SPI_PMIF_MONITOR_RECORD_19_0	((u32)(PMIF_SPI_BASE+0x674))
#define PMIF_SPI_PMIF_MONITOR_RECORD_19_1	((u32)(PMIF_SPI_BASE+0x678))
#define PMIF_SPI_PMIF_MONITOR_RECORD_19_2	((u32)(PMIF_SPI_BASE+0x67C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_19_3	((u32)(PMIF_SPI_BASE+0x680))
#define PMIF_SPI_PMIF_MONITOR_RECORD_19_4	((u32)(PMIF_SPI_BASE+0x684))
#define PMIF_SPI_PMIF_MONITOR_RECORD_20_0	((u32)(PMIF_SPI_BASE+0x688))
#define PMIF_SPI_PMIF_MONITOR_RECORD_20_1	((u32)(PMIF_SPI_BASE+0x68C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_20_2	((u32)(PMIF_SPI_BASE+0x690))
#define PMIF_SPI_PMIF_MONITOR_RECORD_20_3	((u32)(PMIF_SPI_BASE+0x694))
#define PMIF_SPI_PMIF_MONITOR_RECORD_20_4	((u32)(PMIF_SPI_BASE+0x698))
#define PMIF_SPI_PMIF_MONITOR_RECORD_21_0	((u32)(PMIF_SPI_BASE+0x69C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_21_1	((u32)(PMIF_SPI_BASE+0x6A0))
#define PMIF_SPI_PMIF_MONITOR_RECORD_21_2	((u32)(PMIF_SPI_BASE+0x6A4))
#define PMIF_SPI_PMIF_MONITOR_RECORD_21_3	((u32)(PMIF_SPI_BASE+0x6A8))
#define PMIF_SPI_PMIF_MONITOR_RECORD_21_4	((u32)(PMIF_SPI_BASE+0x6AC))
#define PMIF_SPI_PMIF_MONITOR_RECORD_22_0	((u32)(PMIF_SPI_BASE+0x6B0))
#define PMIF_SPI_PMIF_MONITOR_RECORD_22_1	((u32)(PMIF_SPI_BASE+0x6B4))
#define PMIF_SPI_PMIF_MONITOR_RECORD_22_2	((u32)(PMIF_SPI_BASE+0x6B8))
#define PMIF_SPI_PMIF_MONITOR_RECORD_22_3	((u32)(PMIF_SPI_BASE+0x6BC))
#define PMIF_SPI_PMIF_MONITOR_RECORD_22_4	((u32)(PMIF_SPI_BASE+0x6C0))
#define PMIF_SPI_PMIF_MONITOR_RECORD_23_0	((u32)(PMIF_SPI_BASE+0x6C4))
#define PMIF_SPI_PMIF_MONITOR_RECORD_23_1	((u32)(PMIF_SPI_BASE+0x6C8))
#define PMIF_SPI_PMIF_MONITOR_RECORD_23_2	((u32)(PMIF_SPI_BASE+0x6CC))
#define PMIF_SPI_PMIF_MONITOR_RECORD_23_3	((u32)(PMIF_SPI_BASE+0x6D0))
#define PMIF_SPI_PMIF_MONITOR_RECORD_23_4	((u32)(PMIF_SPI_BASE+0x6D4))
#define PMIF_SPI_PMIF_MONITOR_RECORD_24_0	((u32)(PMIF_SPI_BASE+0x6D8))
#define PMIF_SPI_PMIF_MONITOR_RECORD_24_1	((u32)(PMIF_SPI_BASE+0x6DC))
#define PMIF_SPI_PMIF_MONITOR_RECORD_24_2	((u32)(PMIF_SPI_BASE+0x6E0))
#define PMIF_SPI_PMIF_MONITOR_RECORD_24_3	((u32)(PMIF_SPI_BASE+0x6E4))
#define PMIF_SPI_PMIF_MONITOR_RECORD_24_4	((u32)(PMIF_SPI_BASE+0x6E8))
#define PMIF_SPI_PMIF_MONITOR_RECORD_25_0	((u32)(PMIF_SPI_BASE+0x6EC))
#define PMIF_SPI_PMIF_MONITOR_RECORD_25_1	((u32)(PMIF_SPI_BASE+0x6F0))
#define PMIF_SPI_PMIF_MONITOR_RECORD_25_2	((u32)(PMIF_SPI_BASE+0x6F4))
#define PMIF_SPI_PMIF_MONITOR_RECORD_25_3	((u32)(PMIF_SPI_BASE+0x6F8))
#define PMIF_SPI_PMIF_MONITOR_RECORD_25_4	((u32)(PMIF_SPI_BASE+0x6FC))
#define PMIF_SPI_PMIF_MONITOR_RECORD_26_0	((u32)(PMIF_SPI_BASE+0x700))
#define PMIF_SPI_PMIF_MONITOR_RECORD_26_1	((u32)(PMIF_SPI_BASE+0x704))
#define PMIF_SPI_PMIF_MONITOR_RECORD_26_2	((u32)(PMIF_SPI_BASE+0x708))
#define PMIF_SPI_PMIF_MONITOR_RECORD_26_3	((u32)(PMIF_SPI_BASE+0x70C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_26_4	((u32)(PMIF_SPI_BASE+0x710))
#define PMIF_SPI_PMIF_MONITOR_RECORD_27_0	((u32)(PMIF_SPI_BASE+0x714))
#define PMIF_SPI_PMIF_MONITOR_RECORD_27_1	((u32)(PMIF_SPI_BASE+0x718))
#define PMIF_SPI_PMIF_MONITOR_RECORD_27_2	((u32)(PMIF_SPI_BASE+0x71C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_27_3	((u32)(PMIF_SPI_BASE+0x720))
#define PMIF_SPI_PMIF_MONITOR_RECORD_27_4	((u32)(PMIF_SPI_BASE+0x724))
#define PMIF_SPI_PMIF_MONITOR_RECORD_28_0	((u32)(PMIF_SPI_BASE+0x728))
#define PMIF_SPI_PMIF_MONITOR_RECORD_28_1	((u32)(PMIF_SPI_BASE+0x72C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_28_2	((u32)(PMIF_SPI_BASE+0x730))
#define PMIF_SPI_PMIF_MONITOR_RECORD_28_3	((u32)(PMIF_SPI_BASE+0x734))
#define PMIF_SPI_PMIF_MONITOR_RECORD_28_4	((u32)(PMIF_SPI_BASE+0x738))
#define PMIF_SPI_PMIF_MONITOR_RECORD_29_0	((u32)(PMIF_SPI_BASE+0x73C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_29_1	((u32)(PMIF_SPI_BASE+0x740))
#define PMIF_SPI_PMIF_MONITOR_RECORD_29_2	((u32)(PMIF_SPI_BASE+0x744))
#define PMIF_SPI_PMIF_MONITOR_RECORD_29_3	((u32)(PMIF_SPI_BASE+0x748))
#define PMIF_SPI_PMIF_MONITOR_RECORD_29_4	((u32)(PMIF_SPI_BASE+0x74C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_30_0	((u32)(PMIF_SPI_BASE+0x750))
#define PMIF_SPI_PMIF_MONITOR_RECORD_30_1	((u32)(PMIF_SPI_BASE+0x754))
#define PMIF_SPI_PMIF_MONITOR_RECORD_30_2	((u32)(PMIF_SPI_BASE+0x758))
#define PMIF_SPI_PMIF_MONITOR_RECORD_30_3	((u32)(PMIF_SPI_BASE+0x75C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_30_4	((u32)(PMIF_SPI_BASE+0x760))
#define PMIF_SPI_PMIF_MONITOR_RECORD_31_0	((u32)(PMIF_SPI_BASE+0x764))
#define PMIF_SPI_PMIF_MONITOR_RECORD_31_1	((u32)(PMIF_SPI_BASE+0x768))
#define PMIF_SPI_PMIF_MONITOR_RECORD_31_2	((u32)(PMIF_SPI_BASE+0x76C))
#define PMIF_SPI_PMIF_MONITOR_RECORD_31_3	((u32)(PMIF_SPI_BASE+0x770))
#define PMIF_SPI_PMIF_MONITOR_RECORD_31_4	((u32)(PMIF_SPI_BASE+0x774))
#define PMIF_SPI_PMIF_DEBUG_CTRL	((u32)(PMIF_SPI_BASE+0x778))
#define PMIF_SPI_PMIF_BWC_OPTIONS	((u32)(PMIF_SPI_BASE+0x77C))
#define PMIF_SPI_PMIF_RESERVED_0	((u32)(PMIF_SPI_BASE+0x780))
#define PMIF_SPI_PMIF_RESERVED_1	((u32)(PMIF_SPI_BASE+0x784))
#define PMIF_SPI_PMIF_SWINF_0_ACC	((u32)(PMIF_SPI_BASE+0x800))
#define PMIF_SPI_PMIF_SWINF_0_WDATA_31_0	((u32)(PMIF_SPI_BASE+0x804))
#define PMIF_SPI_PMIF_SWINF_0_WDATA_63_32	((u32)(PMIF_SPI_BASE+0x808))
#define PMIF_SPI_PMIF_SWINF_0_WDATA_95_64	((u32)(PMIF_SPI_BASE+0x80C))
#define PMIF_SPI_PMIF_SWINF_0_WDATA_127_96	((u32)(PMIF_SPI_BASE+0x810))
#define PMIF_SPI_PMIF_SWINF_0_RDATA_31_0	((u32)(PMIF_SPI_BASE+0x814))
#define PMIF_SPI_PMIF_SWINF_0_RDATA_63_32	((u32)(PMIF_SPI_BASE+0x818))
#define PMIF_SPI_PMIF_SWINF_0_RDATA_95_64	((u32)(PMIF_SPI_BASE+0x81C))
#define PMIF_SPI_PMIF_SWINF_0_RDATA_127_96	((u32)(PMIF_SPI_BASE+0x820))
#define PMIF_SPI_PMIF_SWINF_0_VLD_CLR	((u32)(PMIF_SPI_BASE+0x824))
#define PMIF_SPI_PMIF_SWINF_0_STA	((u32)(PMIF_SPI_BASE+0x828))
#define PMIF_SPI_PMIF_SWINF_1_ACC	((u32)(PMIF_SPI_BASE+0x840))
#define PMIF_SPI_PMIF_SWINF_1_WDATA_31_0	((u32)(PMIF_SPI_BASE+0x844))
#define PMIF_SPI_PMIF_SWINF_1_WDATA_63_32	((u32)(PMIF_SPI_BASE+0x848))
#define PMIF_SPI_PMIF_SWINF_1_WDATA_95_64	((u32)(PMIF_SPI_BASE+0x84C))
#define PMIF_SPI_PMIF_SWINF_1_WDATA_127_96	((u32)(PMIF_SPI_BASE+0x850))
#define PMIF_SPI_PMIF_SWINF_1_RDATA_31_0	((u32)(PMIF_SPI_BASE+0x854))
#define PMIF_SPI_PMIF_SWINF_1_RDATA_63_32	((u32)(PMIF_SPI_BASE+0x858))
#define PMIF_SPI_PMIF_SWINF_1_RDATA_95_64	((u32)(PMIF_SPI_BASE+0x85C))
#define PMIF_SPI_PMIF_SWINF_1_RDATA_127_96	((u32)(PMIF_SPI_BASE+0x860))
#define PMIF_SPI_PMIF_SWINF_1_VLD_CLR	((u32)(PMIF_SPI_BASE+0x864))
#define PMIF_SPI_PMIF_SWINF_1_STA	((u32)(PMIF_SPI_BASE+0x868))
#define PMIF_SPI_PMIF_SWINF_2_ACC	((u32)(PMIF_SPI_BASE+0x880))
#define PMIF_SPI_PMIF_SWINF_2_WDATA_31_0	((u32)(PMIF_SPI_BASE+0x884))
#define PMIF_SPI_PMIF_SWINF_2_WDATA_63_32	((u32)(PMIF_SPI_BASE+0x888))
#define PMIF_SPI_PMIF_SWINF_2_WDATA_95_64	((u32)(PMIF_SPI_BASE+0x88C))
#define PMIF_SPI_PMIF_SWINF_2_WDATA_127_96	((u32)(PMIF_SPI_BASE+0x890))
#define PMIF_SPI_PMIF_SWINF_2_RDATA_31_0	((u32)(PMIF_SPI_BASE+0x894))
#define PMIF_SPI_PMIF_SWINF_2_RDATA_63_32	((u32)(PMIF_SPI_BASE+0x898))
#define PMIF_SPI_PMIF_SWINF_2_RDATA_95_64	((u32)(PMIF_SPI_BASE+0x89C))
#define PMIF_SPI_PMIF_SWINF_2_RDATA_127_96	((u32)(PMIF_SPI_BASE+0x8A0))
#define PMIF_SPI_PMIF_SWINF_2_VLD_CLR	((u32)(PMIF_SPI_BASE+0x8A4))
#define PMIF_SPI_PMIF_SWINF_2_STA	((u32)(PMIF_SPI_BASE+0x8A8))
#define PMIF_SPI_PMIF_SWINF_3_ACC	((u32)(PMIF_SPI_BASE+0x8C0))
#define PMIF_SPI_PMIF_SWINF_3_WDATA_31_0	((u32)(PMIF_SPI_BASE+0x8C4))
#define PMIF_SPI_PMIF_SWINF_3_WDATA_63_32	((u32)(PMIF_SPI_BASE+0x8C8))
#define PMIF_SPI_PMIF_SWINF_3_WDATA_95_64	((u32)(PMIF_SPI_BASE+0x8CC))
#define PMIF_SPI_PMIF_SWINF_3_WDATA_127_96	((u32)(PMIF_SPI_BASE+0x8D0))
#define PMIF_SPI_PMIF_SWINF_3_RDATA_31_0	((u32)(PMIF_SPI_BASE+0x8D4))
#define PMIF_SPI_PMIF_SWINF_3_RDATA_63_32	((u32)(PMIF_SPI_BASE+0x8D8))
#define PMIF_SPI_PMIF_SWINF_3_RDATA_95_64	((u32)(PMIF_SPI_BASE+0x8DC))
#define PMIF_SPI_PMIF_SWINF_3_RDATA_127_96	((u32)(PMIF_SPI_BASE+0x8E0))
#define PMIF_SPI_PMIF_SWINF_3_VLD_CLR	((u32)(PMIF_SPI_BASE+0x8E4))
#define PMIF_SPI_PMIF_SWINF_3_STA	((u32)(PMIF_SPI_BASE+0x8E8))

// APB Module pmicspi_mst
#define PMICSPI_MST_SWRST	((u32)(PMICSPI_MST_BASE+0x0))
#define PMICSPI_MST_DCM_CTRL	((u32)(PMICSPI_MST_BASE+0x4))
#define PMICSPI_MST_DCM_STA	((u32)(PMICSPI_MST_BASE+0x8))
#define PMICSPI_MST_OTHER_CK_DCM_EN	((u32)(PMICSPI_MST_BASE+0xC))
#define PMICSPI_MST_OTHER_BUSY_STA_0	((u32)(PMICSPI_MST_BASE+0x10))
#define PMICSPI_MST_SPIWRAP_EN	((u32)(PMICSPI_MST_BASE+0x14))
#define PMICSPI_MST_SPIWRAP_STA_0	((u32)(PMICSPI_MST_BASE+0x18))
#define PMICSPI_MST_SPIWRAP_STA_1	((u32)(PMICSPI_MST_BASE+0x1C))
#define PMICSPI_MST_SPIMAN_EN	((u32)(PMICSPI_MST_BASE+0x20))
#define PMICSPI_MST_SPIMAN_ACC	((u32)(PMICSPI_MST_BASE+0x24))
#define PMICSPI_MST_SPIMAN_RDATA	((u32)(PMICSPI_MST_BASE+0x28))
#define PMICSPI_MST_SPIMAN_VLD_CLR	((u32)(PMICSPI_MST_BASE+0x2C))
#define PMICSPI_MST_SPIMAN_STA	((u32)(PMICSPI_MST_BASE+0x30))
#define PMICSPI_MST_SPIMUX_SEL	((u32)(PMICSPI_MST_BASE+0x34))
#define PMICSPI_MST_SPIMUX_STA	((u32)(PMICSPI_MST_BASE+0x38))
#define PMICSPI_MST_SPICIPHER_CTRL	((u32)(PMICSPI_MST_BASE+0x3C))
#define PMICSPI_MST_SPICIPHER_STA	((u32)(PMICSPI_MST_BASE+0x40))
#define PMICSPI_MST_DIO_EN	((u32)(PMICSPI_MST_BASE+0x44))
#define PMICSPI_MST_RDDMY	((u32)(PMICSPI_MST_BASE+0x48))
#define PMICSPI_MST_CSLEXT_WRITE	((u32)(PMICSPI_MST_BASE+0x4C))
#define PMICSPI_MST_CSLEXT_READ	((u32)(PMICSPI_MST_BASE+0x50))
#define PMICSPI_MST_CSHEXT_WRITE	((u32)(PMICSPI_MST_BASE+0x54))
#define PMICSPI_MST_CSHEXT_READ	((u32)(PMICSPI_MST_BASE+0x58))
#define PMICSPI_MST_EXT_CK_WRITE	((u32)(PMICSPI_MST_BASE+0x5C))
#define PMICSPI_MST_EXT_CK_READ	((u32)(PMICSPI_MST_BASE+0x60))
#define PMICSPI_MST_SI_SAMPLING_CTRL	((u32)(PMICSPI_MST_BASE+0x64))
#define PMICSPI_MST_SI_SAMPLING_CTRL_1	((u32)(PMICSPI_MST_BASE+0x68))
#define PMICSPI_MST_SI_SAMPLING_CTRL_2	((u32)(PMICSPI_MST_BASE+0x6C))
#define PMICSPI_MST_SI_SAMPLING_CTRL_3	((u32)(PMICSPI_MST_BASE+0x70))
#define PMICSPI_MST_SI_SAMPLING_CTRL_ULPOSC	((u32)(PMICSPI_MST_BASE+0x74))
#define PMICSPI_MST_DEBUG_CTRL	((u32)(PMICSPI_MST_BASE+0x78))
#define PMICSPI_MST_RESERVED_0	((u32)(PMICSPI_MST_BASE+0x7C))
#define PMICSPI_MST_RESERVED_1	((u32)(PMICSPI_MST_BASE+0x80))
#define PMICSPI_MST_FT_CTRL	((u32)(PMICSPI_MST_BASE+0x84))
#define PMICSPI_MST_FT_CTRL_CHK	((u32)(PMICSPI_MST_BASE+0x88))

// APB Module pmif_mpu
#define PMIF_SPI_PMIF_MPU_CTRL	((u32)(PMIF_SPI_BASE+0x900))
#define PMIF_SPI_PMIF_PMIC_RGN_EN	((u32)(PMIF_SPI_BASE+0x904))
#define PMIF_SPI_PMIF_PMIC_RGN_0_START	((u32)(PMIF_SPI_BASE+0x908))
#define PMIF_SPI_PMIF_PMIC_RGN_0_END	((u32)(PMIF_SPI_BASE+0x90C))
#define PMIF_SPI_PMIF_PMIC_RGN_1_START	((u32)(PMIF_SPI_BASE+0x910))
#define PMIF_SPI_PMIF_PMIC_RGN_1_END	((u32)(PMIF_SPI_BASE+0x914))
#define PMIF_SPI_PMIF_PMIC_RGN_2_START	((u32)(PMIF_SPI_BASE+0x918))
#define PMIF_SPI_PMIF_PMIC_RGN_2_END	((u32)(PMIF_SPI_BASE+0x91C))
#define PMIF_SPI_PMIF_PMIC_RGN_3_START	((u32)(PMIF_SPI_BASE+0x920))
#define PMIF_SPI_PMIF_PMIC_RGN_3_END	((u32)(PMIF_SPI_BASE+0x924))
#define PMIF_SPI_PMIF_PMIC_RGN_0_PER	((u32)(PMIF_SPI_BASE+0x928))
#define PMIF_SPI_PMIF_PMIC_RGN_1_PER	((u32)(PMIF_SPI_BASE+0x92C))
#define PMIF_SPI_PMIF_PMIC_RGN_2_PER	((u32)(PMIF_SPI_BASE+0x930))
#define PMIF_SPI_PMIF_PMIC_RGN_3_PER	((u32)(PMIF_SPI_BASE+0x934))
#define PMIF_SPI_PMIF_PMIC_OTHERS_PER	((u32)(PMIF_SPI_BASE+0x938))
#define PMIF_SPI_PMIF_SWINF_0_PER	((u32)(PMIF_SPI_BASE+0x93C))
#define PMIF_SPI_PMIF_SWINF_1_PER	((u32)(PMIF_SPI_BASE+0x940))
#define PMIF_SPI_PMIF_SWINF_2_PER	((u32)(PMIF_SPI_BASE+0x944))
#define PMIF_SPI_PMIF_SWINF_3_PER	((u32)(PMIF_SPI_BASE+0x948))
#define PMIF_SPI_PMIF_PMIF_OTHERS_PER	((u32)(PMIF_SPI_BASE+0x94C))
#define PMIF_SPI_PMIF_PMIC_ACC_VIO_INFO_0	((u32)(PMIF_SPI_BASE+0x950))
#define PMIF_SPI_PMIF_PMIC_ACC_VIO_INFO_1	((u32)(PMIF_SPI_BASE+0x954))
#define PMIF_SPI_PMIF_PMIC_ACC_VIO_INFO_2	((u32)(PMIF_SPI_BASE+0x958))
#define PMIF_SPI_PMIF_PMIC_ACC_VIO_INFO_3	((u32)(PMIF_SPI_BASE+0x95C))
#define PMIF_SPI_PMIF_PMIC_ACC_VIO_INFO_4	((u32)(PMIF_SPI_BASE+0x960))
#define PMIF_SPI_PMIF_PMIC_ACC_VIO_INFO_5	((u32)(PMIF_SPI_BASE+0x964))
#define PMIF_SPI_PMIF_PMIC_ACC_SCP_VIO_INFO_0	((u32)(PMIF_SPI_BASE+0x968))
#define PMIF_SPI_PMIF_PMIC_ACC_SCP_VIO_INFO_1	((u32)(PMIF_SPI_BASE+0x96C))
#define PMIF_SPI_PMIF_PMIC_ACC_SCP_VIO_INFO_2	((u32)(PMIF_SPI_BASE+0x970))
#define PMIF_SPI_PMIF_PMIC_ACC_SCP_VIO_INFO_3	((u32)(PMIF_SPI_BASE+0x974))
#define PMIF_SPI_PMIF_PMIC_ACC_SCP_VIO_INFO_4	((u32)(PMIF_SPI_BASE+0x978))
#define PMIF_SPI_PMIF_PMIC_ACC_SCP_VIO_INFO_5	((u32)(PMIF_SPI_BASE+0x97C))
#define PMIF_SPI_PMIF_PMIF_ACC_VIO_INFO_0	((u32)(PMIF_SPI_BASE+0x980))
#define PMIF_SPI_PMIF_PMIF_ACC_VIO_INFO_1	((u32)(PMIF_SPI_BASE+0x984))
#define PMIF_SPI_PMIF_PMIF_ACC_VIO_INFO_2	((u32)(PMIF_SPI_BASE+0x988))
#define PMIF_SPI_PMIF_PMIC_ACC_SSPM_VIO_INFO_0	((u32)(PMIF_SPI_BASE+0x98C))
#define PMIF_SPI_PMIF_PMIC_ACC_SSPM_VIO_INFO_1	((u32)(PMIF_SPI_BASE+0x990))
#define PMIF_SPI_PMIF_PMIC_ACC_SSPM_VIO_INFO_2	((u32)(PMIF_SPI_BASE+0x994))
#define PMIF_SPI_PMIF_PMIC_ACC_SSPM_VIO_INFO_3	((u32)(PMIF_SPI_BASE+0x998))
#define PMIF_SPI_PMIF_PMIC_ACC_SSPM_VIO_INFO_4	((u32)(PMIF_SPI_BASE+0x99C))
#define PMIF_SPI_PMIF_PMIC_ACC_SSPM_VIO_INFO_5	((u32)(PMIF_SPI_BASE+0x9A0))
#define PMIF_SPI_PMIF_PMIC_ALL_VIO_INFO_0	((u32)(PMIF_SPI_BASE+0x9A4))
#define PMIF_SPI_PMIF_PMIC_ALL_VIO_INFO_1	((u32)(PMIF_SPI_BASE+0x9A8))
#define PMIF_SPI_PMIF_PMIC_ALL_VIO_INFO_2	((u32)(PMIF_SPI_BASE+0x9AC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_EN		((u32)(PMIF_SPI_BASE+0x9B0))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_0_START	((u32)(PMIF_SPI_BASE+0x9B4))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_0_END	((u32)(PMIF_SPI_BASE+0x9B8))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_1_START	((u32)(PMIF_SPI_BASE+0x9BC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_1_END	((u32)(PMIF_SPI_BASE+0x9C0))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_2_START	((u32)(PMIF_SPI_BASE+0x9C4))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_2_END	((u32)(PMIF_SPI_BASE+0x9C8))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_3_START	((u32)(PMIF_SPI_BASE+0x9CC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_3_END	((u32)(PMIF_SPI_BASE+0x9D0))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_4_START	((u32)(PMIF_SPI_BASE+0x9D4))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_4_END	((u32)(PMIF_SPI_BASE+0x9D8))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_5_START	((u32)(PMIF_SPI_BASE+0x9DC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_5_END	((u32)(PMIF_SPI_BASE+0x9E0))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_6_START	((u32)(PMIF_SPI_BASE+0x9E4))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_6_END	((u32)(PMIF_SPI_BASE+0x9E8))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_7_START	((u32)(PMIF_SPI_BASE+0x9EC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_7_END	((u32)(PMIF_SPI_BASE+0x9F0))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_8_START	((u32)(PMIF_SPI_BASE+0x9F4))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_8_END	((u32)(PMIF_SPI_BASE+0x9F8))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_9_START	((u32)(PMIF_SPI_BASE+0x9FC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_9_END	((u32)(PMIF_SPI_BASE+0xA00))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_10_START	((u32)(PMIF_SPI_BASE+0xA04))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_10_END	((u32)(PMIF_SPI_BASE+0xA08))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_11_START	((u32)(PMIF_SPI_BASE+0xA0C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_11_END	((u32)(PMIF_SPI_BASE+0xA10))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_12_START	((u32)(PMIF_SPI_BASE+0xA14))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_12_END	((u32)(PMIF_SPI_BASE+0xA18))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_13_START	((u32)(PMIF_SPI_BASE+0xA1C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_13_END	((u32)(PMIF_SPI_BASE+0xA20))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_14_START	((u32)(PMIF_SPI_BASE+0xA24))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_14_END	((u32)(PMIF_SPI_BASE+0xA28))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_15_START	((u32)(PMIF_SPI_BASE+0xA2C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_15_END	((u32)(PMIF_SPI_BASE+0xA30))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_16_START	((u32)(PMIF_SPI_BASE+0xA34))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_16_END	((u32)(PMIF_SPI_BASE+0xA38))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_17_START	((u32)(PMIF_SPI_BASE+0xA3C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_17_END	((u32)(PMIF_SPI_BASE+0xA40))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_18_START	((u32)(PMIF_SPI_BASE+0xA44))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_18_END	((u32)(PMIF_SPI_BASE+0xA48))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_19_START	((u32)(PMIF_SPI_BASE+0xA4C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_19_END	((u32)(PMIF_SPI_BASE+0xA50))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_20_START	((u32)(PMIF_SPI_BASE+0xA54))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_20_END	((u32)(PMIF_SPI_BASE+0xA58))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_21_START	((u32)(PMIF_SPI_BASE+0xA5C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_21_END	((u32)(PMIF_SPI_BASE+0xA60))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_22_START	((u32)(PMIF_SPI_BASE+0xA64))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_22_END	((u32)(PMIF_SPI_BASE+0xA68))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_23_START	((u32)(PMIF_SPI_BASE+0xA6C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_23_END	((u32)(PMIF_SPI_BASE+0xA70))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_24_START	((u32)(PMIF_SPI_BASE+0xA74))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_24_END	((u32)(PMIF_SPI_BASE+0xA78))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_25_START	((u32)(PMIF_SPI_BASE+0xA7C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_25_END	((u32)(PMIF_SPI_BASE+0xA80))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_26_START	((u32)(PMIF_SPI_BASE+0xA84))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_26_END	((u32)(PMIF_SPI_BASE+0xA88))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_27_START	((u32)(PMIF_SPI_BASE+0xA8C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_27_END	((u32)(PMIF_SPI_BASE+0xA90))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_28_START	((u32)(PMIF_SPI_BASE+0xA94))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_28_END	((u32)(PMIF_SPI_BASE+0xA98))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_29_START	((u32)(PMIF_SPI_BASE+0xA9C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_29_END	((u32)(PMIF_SPI_BASE+0xAA0))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_30_START	((u32)(PMIF_SPI_BASE+0xAA4))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_30_END	((u32)(PMIF_SPI_BASE+0xAA8))
#define PMIF_SPI_PMIF_PMIC_ALL_INVID_SLVID	((u32)(PMIF_SPI_BASE+0xAAC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_0_PER0	((u32)(PMIF_SPI_BASE+0xAB0))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_0_PER1	((u32)(PMIF_SPI_BASE+0xAB4))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_1_PER0	((u32)(PMIF_SPI_BASE+0xAB8))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_1_PER1	((u32)(PMIF_SPI_BASE+0xABC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_2_PER0	((u32)(PMIF_SPI_BASE+0xAC0))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_2_PER1	((u32)(PMIF_SPI_BASE+0xAC4))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_3_PER0	((u32)(PMIF_SPI_BASE+0xAC8))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_3_PER1	((u32)(PMIF_SPI_BASE+0xACC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_4_PER0	((u32)(PMIF_SPI_BASE+0xAD0))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_4_PER1	((u32)(PMIF_SPI_BASE+0xAD4))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_5_PER0	((u32)(PMIF_SPI_BASE+0xAD8))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_5_PER1	((u32)(PMIF_SPI_BASE+0xADC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_6_PER0	((u32)(PMIF_SPI_BASE+0xAE0))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_6_PER1	((u32)(PMIF_SPI_BASE+0xAE4))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_7_PER0	((u32)(PMIF_SPI_BASE+0xAE8))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_7_PER1	((u32)(PMIF_SPI_BASE+0xAEC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_8_PER0	((u32)(PMIF_SPI_BASE+0xAF0))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_8_PER1	((u32)(PMIF_SPI_BASE+0xAF4))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_9_PER0	((u32)(PMIF_SPI_BASE+0xAF8))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_9_PER1	((u32)(PMIF_SPI_BASE+0xAFC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_10_PER0	((u32)(PMIF_SPI_BASE+0xB00))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_10_PER1	((u32)(PMIF_SPI_BASE+0xB04))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_11_PER0	((u32)(PMIF_SPI_BASE+0xB08))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_11_PER1	((u32)(PMIF_SPI_BASE+0xB0C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_12_PER0	((u32)(PMIF_SPI_BASE+0xB10))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_12_PER1	((u32)(PMIF_SPI_BASE+0xB14))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_13_PER0	((u32)(PMIF_SPI_BASE+0xB18))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_13_PER1	((u32)(PMIF_SPI_BASE+0xB1C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_14_PER0	((u32)(PMIF_SPI_BASE+0xB20))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_14_PER1	((u32)(PMIF_SPI_BASE+0xB24))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_15_PER0	((u32)(PMIF_SPI_BASE+0xB28))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_15_PER1	((u32)(PMIF_SPI_BASE+0xB2C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_16_PER0	((u32)(PMIF_SPI_BASE+0xB30))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_16_PER1	((u32)(PMIF_SPI_BASE+0xB34))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_17_PER0	((u32)(PMIF_SPI_BASE+0xB38))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_17_PER1	((u32)(PMIF_SPI_BASE+0xB3C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_18_PER0	((u32)(PMIF_SPI_BASE+0xB40))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_18_PER1	((u32)(PMIF_SPI_BASE+0xB44))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_19_PER0	((u32)(PMIF_SPI_BASE+0xB48))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_19_PER1	((u32)(PMIF_SPI_BASE+0xB4C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_20_PER0	((u32)(PMIF_SPI_BASE+0xB50))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_20_PER1	((u32)(PMIF_SPI_BASE+0xB54))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_21_PER0	((u32)(PMIF_SPI_BASE+0xB58))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_21_PER1	((u32)(PMIF_SPI_BASE+0xB5C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_22_PER0	((u32)(PMIF_SPI_BASE+0xB60))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_22_PER1	((u32)(PMIF_SPI_BASE+0xB64))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_23_PER0	((u32)(PMIF_SPI_BASE+0xB68))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_23_PER1	((u32)(PMIF_SPI_BASE+0xB6C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_24_PER0	((u32)(PMIF_SPI_BASE+0xB70))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_24_PER1	((u32)(PMIF_SPI_BASE+0xB74))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_25_PER0	((u32)(PMIF_SPI_BASE+0xB78))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_25_PER1	((u32)(PMIF_SPI_BASE+0xB7C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_26_PER0	((u32)(PMIF_SPI_BASE+0xB80))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_26_PER1	((u32)(PMIF_SPI_BASE+0xB84))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_27_PER0	((u32)(PMIF_SPI_BASE+0xB88))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_27_PER1	((u32)(PMIF_SPI_BASE+0xB8C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_28_PER0	((u32)(PMIF_SPI_BASE+0xB90))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_28_PER1	((u32)(PMIF_SPI_BASE+0xB94))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_29_PER0	((u32)(PMIF_SPI_BASE+0xB98))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_29_PER1	((u32)(PMIF_SPI_BASE+0xB9C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_30_PER0	((u32)(PMIF_SPI_BASE+0xBA0))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_30_PER1	((u32)(PMIF_SPI_BASE+0xBA4))
#define PMIF_SPI_PMIF_PMIC_ALL_OTHERS_PER0	((u32)(PMIF_SPI_BASE+0xBA8))
#define PMIF_SPI_PMIF_PMIC_ALL_OTHERS_PER1	((u32)(PMIF_SPI_BASE+0xBAC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_0_CMD_PER0	((u32)(PMIF_SPI_BASE+0xBB0))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_0_CMD_PER1	((u32)(PMIF_SPI_BASE+0xBB4))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_0_CMD_PER2	((u32)(PMIF_SPI_BASE+0xBB8))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_1_CMD_PER0	((u32)(PMIF_SPI_BASE+0xBBC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_1_CMD_PER1	((u32)(PMIF_SPI_BASE+0xBC0))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_1_CMD_PER2	((u32)(PMIF_SPI_BASE+0xBC4))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_2_CMD_PER0	((u32)(PMIF_SPI_BASE+0xBC8))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_2_CMD_PER1	((u32)(PMIF_SPI_BASE+0xBCC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_2_CMD_PER2	((u32)(PMIF_SPI_BASE+0xBD0))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_3_CMD_PER0	((u32)(PMIF_SPI_BASE+0xBD4))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_3_CMD_PER1	((u32)(PMIF_SPI_BASE+0xBD8))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_3_CMD_PER2	((u32)(PMIF_SPI_BASE+0xBDC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_4_CMD_PER0	((u32)(PMIF_SPI_BASE+0xBE0))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_4_CMD_PER1	((u32)(PMIF_SPI_BASE+0xBE4))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_4_CMD_PER2	((u32)(PMIF_SPI_BASE+0xBE8))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_5_CMD_PER0	((u32)(PMIF_SPI_BASE+0xBEC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_5_CMD_PER1	((u32)(PMIF_SPI_BASE+0xBF0))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_5_CMD_PER2	((u32)(PMIF_SPI_BASE+0xBF4))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_6_CMD_PER0	((u32)(PMIF_SPI_BASE+0xBF8))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_6_CMD_PER1	((u32)(PMIF_SPI_BASE+0xBFC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_6_CMD_PER2	((u32)(PMIF_SPI_BASE+0xC00))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_7_CMD_PER0	((u32)(PMIF_SPI_BASE+0xC04))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_7_CMD_PER1	((u32)(PMIF_SPI_BASE+0xC08))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_7_CMD_PER2	((u32)(PMIF_SPI_BASE+0xC0C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_8_CMD_PER0	((u32)(PMIF_SPI_BASE+0xC10))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_8_CMD_PER1	((u32)(PMIF_SPI_BASE+0xC14))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_8_CMD_PER2	((u32)(PMIF_SPI_BASE+0xC18))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_9_CMD_PER0	((u32)(PMIF_SPI_BASE+0xC1C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_9_CMD_PER1	((u32)(PMIF_SPI_BASE+0xC20))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_9_CMD_PER2	((u32)(PMIF_SPI_BASE+0xC24))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_10_CMD_PER0	((u32)(PMIF_SPI_BASE+0xC28))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_10_CMD_PER1	((u32)(PMIF_SPI_BASE+0xC2C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_10_CMD_PER2	((u32)(PMIF_SPI_BASE+0xC30))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_11_CMD_PER0	((u32)(PMIF_SPI_BASE+0xC34))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_11_CMD_PER1	((u32)(PMIF_SPI_BASE+0xC38))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_11_CMD_PER2	((u32)(PMIF_SPI_BASE+0xC3C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_12_CMD_PER0	((u32)(PMIF_SPI_BASE+0xC40))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_12_CMD_PER1	((u32)(PMIF_SPI_BASE+0xC44))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_12_CMD_PER2	((u32)(PMIF_SPI_BASE+0xC48))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_13_CMD_PER0	((u32)(PMIF_SPI_BASE+0xC4C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_13_CMD_PER1	((u32)(PMIF_SPI_BASE+0xC50))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_13_CMD_PER2	((u32)(PMIF_SPI_BASE+0xC54))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_14_CMD_PER0	((u32)(PMIF_SPI_BASE+0xC58))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_14_CMD_PER1	((u32)(PMIF_SPI_BASE+0xC5C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_14_CMD_PER2	((u32)(PMIF_SPI_BASE+0xC60))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_15_CMD_PER0	((u32)(PMIF_SPI_BASE+0xC64))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_15_CMD_PER1	((u32)(PMIF_SPI_BASE+0xC68))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_15_CMD_PER2	((u32)(PMIF_SPI_BASE+0xC6C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_16_CMD_PER0	((u32)(PMIF_SPI_BASE+0xC70))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_16_CMD_PER1	((u32)(PMIF_SPI_BASE+0xC74))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_16_CMD_PER2	((u32)(PMIF_SPI_BASE+0xC78))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_17_CMD_PER0	((u32)(PMIF_SPI_BASE+0xC7C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_17_CMD_PER1	((u32)(PMIF_SPI_BASE+0xC80))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_17_CMD_PER2	((u32)(PMIF_SPI_BASE+0xC84))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_18_CMD_PER0	((u32)(PMIF_SPI_BASE+0xC88))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_18_CMD_PER1	((u32)(PMIF_SPI_BASE+0xC8C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_18_CMD_PER2	((u32)(PMIF_SPI_BASE+0xC90))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_19_CMD_PER0	((u32)(PMIF_SPI_BASE+0xC94))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_19_CMD_PER1	((u32)(PMIF_SPI_BASE+0xC98))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_19_CMD_PER2	((u32)(PMIF_SPI_BASE+0xC9C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_20_CMD_PER0	((u32)(PMIF_SPI_BASE+0xCA0))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_20_CMD_PER1	((u32)(PMIF_SPI_BASE+0xCA4))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_20_CMD_PER2	((u32)(PMIF_SPI_BASE+0xCA8))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_21_CMD_PER0	((u32)(PMIF_SPI_BASE+0xCAC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_21_CMD_PER1	((u32)(PMIF_SPI_BASE+0xCB0))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_21_CMD_PER2	((u32)(PMIF_SPI_BASE+0xCB4))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_22_CMD_PER0	((u32)(PMIF_SPI_BASE+0xCB8))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_22_CMD_PER1	((u32)(PMIF_SPI_BASE+0xCBC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_22_CMD_PER2	((u32)(PMIF_SPI_BASE+0xCC0))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_23_CMD_PER0	((u32)(PMIF_SPI_BASE+0xCC4))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_23_CMD_PER1	((u32)(PMIF_SPI_BASE+0xCC8))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_23_CMD_PER2	((u32)(PMIF_SPI_BASE+0xCCC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_24_CMD_PER0	((u32)(PMIF_SPI_BASE+0xCD0))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_24_CMD_PER1	((u32)(PMIF_SPI_BASE+0xCD4))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_24_CMD_PER2	((u32)(PMIF_SPI_BASE+0xCD8))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_25_CMD_PER0	((u32)(PMIF_SPI_BASE+0xCDC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_25_CMD_PER1	((u32)(PMIF_SPI_BASE+0xCE0))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_25_CMD_PER2	((u32)(PMIF_SPI_BASE+0xCE4))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_26_CMD_PER0	((u32)(PMIF_SPI_BASE+0xCE8))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_26_CMD_PER1	((u32)(PMIF_SPI_BASE+0xCEC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_26_CMD_PER2	((u32)(PMIF_SPI_BASE+0xCF0))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_27_CMD_PER0	((u32)(PMIF_SPI_BASE+0xCF4))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_27_CMD_PER1	((u32)(PMIF_SPI_BASE+0xCF8))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_27_CMD_PER2	((u32)(PMIF_SPI_BASE+0xCFC))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_28_CMD_PER0	((u32)(PMIF_SPI_BASE+0xD00))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_28_CMD_PER1	((u32)(PMIF_SPI_BASE+0xD04))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_28_CMD_PER2	((u32)(PMIF_SPI_BASE+0xD08))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_29_CMD_PER0	((u32)(PMIF_SPI_BASE+0xD0C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_29_CMD_PER1	((u32)(PMIF_SPI_BASE+0xD10))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_29_CMD_PER2	((u32)(PMIF_SPI_BASE+0xD14))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_30_CMD_PER0	((u32)(PMIF_SPI_BASE+0xD18))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_30_CMD_PER1	((u32)(PMIF_SPI_BASE+0xD1C))
#define PMIF_SPI_PMIF_PMIC_ALL_RGN_30_CMD_PER2	((u32)(PMIF_SPI_BASE+0xD20))
#define PMIF_SPI_PMIF_PMIC_ALL_OTHERS_CMD_PER0	((u32)(PMIF_SPI_BASE+0xD24))
#define PMIF_SPI_PMIF_PMIC_ALL_OTHERS_CMD_PER1	((u32)(PMIF_SPI_BASE+0xD28))
#define PMIF_SPI_PMIF_PMIC_ALL_OTHERS_CMD_PER2	((u32)(PMIF_SPI_BASE+0xD2C))
#endif //__PMIC_WRAP_REGS_H__

